The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of information stored in critical processor resources.
To protect against soft errors, which may cause faulty system operations, modern microprocessors often use parity or Error Correcting Code (ECC) check bits to protect large memory structure such as caches, memory queues, and buffers. While parity and ECC check bits are effective means for combating soft errors, both are expensive in terms of the silicon area for implementation, timing impact, and power consumption. Another drawback to the use of parity or ECC check bits is that the consumed data must be explicitly read out from the memory structures before the parity of the data can be computed. However, not all critical resources in high performance microprocessors that must be protected have this property. In certain critical processor resources, the data can be consumed without being read out explicitly. For example, in a model specific register (MSR) that contains configuration data, the data are often consumed without explicitly being read out.
As another example, Intel(copyright) Architecture 64-bit (IA-64) processors often use a technique called pre-validated Region Identification (RID) and pre-validated protection key to speed up the address translation process. IA-64 processors are manufactured by Intel Corporation of Santa Clara, Calif. In the prevalidation scheme,
(1) the register index of the RID or protection key to be updated is used to disable all entries with a matching register index in the translation lookaside buffer (TLB), and
(2) the new content of the region ID or protection key is then used to enable any matching entry in the TLB.
Only the enabled entries participate during the address translation process. The disabled entries are not removed and can be later re-enabled. Effectively, pre-validation removes the need to compare the RID and protection key during the address translation process. In this way, the address translation processor may be sped up. A side-effect of prevalidation is to turn a frequently used critical resource into an infrequently used critical resource. If any soft error happens to the RID and/or the protection key in the TLB, the processor will operate incorrectly because the RID and/or the protection key may be corrupted.
Therefore what is needed is an efficient apparatus and/or method to protect these infrequently used critical processor resources, such as, for example, the MSR and the pre-validated RIDs and protection keys in the TLB.